Hi everyone,
Having problem with these questions, can someone help me please.
Using the JK FF, design a ripple counter capable of implementing the counting sequence as below:
F(x)={0,1,2,3,4,6,7} and repeats itself
a) Explain the workings of the circuit with special emphasis on the additional circuit required to reset the counter.
b) How many bits are required to implement this counter? Show calculations to justify your answers.
c) What is the maximum frequency of the clock pulse permitted to enter this system, in order for the output to have the correct answer? Explain your answer by providing detailed calculation. (Tips: You may refer to the datasheet for the chip used to implement this function)
d) What are the limitations of this ripple counter?
e) Suggest a way to overcome the limitations.
Thank you. | 
